Design of a Decimator Filter for Novel Sigma-Delta Modulator

In this paper, the designing of decimation filter for sigma-delta (∑-∆) ADC having different oversampling ratio (OSR) is described. The decimation filter perform the operation of down sampling of a high frequency, low resolution signal to Nyquist rate, high resolution digital output. The design of a decimation filter is projected that employs IIR-FIR structure; second order Cascaded Integrator Comb (CIC) filters. This approach eliminates the need for multiplication, requires a maximum clock frequency equal to the sampling. Specifications of decimation filter are dependent upon the overall specification from Σ-Δ A/D converter with sampling frequency 5 MHz. The design implements a decimation ratio of 16, 64 allows a maximum resolution of 9,13 bits in the output of the filter respectively and implemented in 0.25μm CMOS technology. The overall objective is to optimize the decimator in terms of performance and reliability .This paper examines the practical design criteria for implementing the decimator in ∑-∆ ADC.